Intro

FPGA technology is a viable option for many applications and offers a lot of potential, but many think that the entry hurdle is high, and programming is complex and labo

• AMD SoC module
• Base board
• USB camera
• Cooling solution
• Cables & Power supply
• Micro SD card

The extensive and in-detail documentation makes the assembly and compilation of the provided AI example demos a snap.

Also two example demos are included – with all sources available:

• AI face detection
• Image classification 

They are based on ResNet50 and AMD Vitis AI. To run them, a few easy steps are all it takes:

1. Assemble and connect the board with your PC and a monitor
2. Open a serial port connection to the Design-in Kit
3. Log in as root/root
4. Start the demo with the command: facedetect
5. The live video of the USB camera is displayed on the monitor

Get the Resources to Know How

The Design-in Kit user manuals explain step-by-step how to compile the example demos from the sources and provide a base for your own projects. To shorten time-to-market further, Enclustra offers broad design-in support for their products and a comprehensive ecosystem, offering all required hardware, software and support materials. Detailed documentation and reference designs make it easy to get started. A user manual, user schematics, a 3D model, PCB footprints, differential I/O net length tables and the Linux-based Board Support Package (BSP) are all provided.

Following manuals and software are available for download for owner of the kits:

            ✔       Design-in kit quick start guide

            ✔       Design-in kit user manual

            ✔       User manuals for the module and base board

            ✔       Reference design

            ✔       PetaLinux board support package (BSP)

            ✔       Buildroot-based Linux BSP

            ✔       Module pin connection guidelines

            ✔       Master pinout

            ✔       Footprints

            ✔       3D model (STEP)

            ✔       IO net length

            ✔       User schematics

            ✔       Altium design files (base board)

            ✔       Application notes

Be it image processing, machine vision, test & measurement, communication or medical: With an Enclustra System-on-Module, the development time can be halved. Start your project today!

Get to Market Faster with IP Solutions

DSP systems, with a few clicks
The Universal DSP Library provides efficient FPGA implementations of the most common digital signal processing components, such as FIR and CIC filters, mixers, CORDIC and function approximations. It also provides the necessary glue logic needed to connect DSP systems together, such as multiplexers, stream splitters, buffers, TDM-parallel converters and fixed-point format converters.

Streaming, made simple
The Enclustra FPGA Manager IP Solution enables simple and efficient data transfer between a host PC and an FPGA via USB 3.0, Gigabit Ethernet or PCI Express. The solution includes a host software library (DLL) and an IP core for the FPGA. The user application communicates with the FPGA via a simple API with read/write commands that hide the complexity of the underlying protocol. Both streaming and memory mapped accesses are supported.

Motion Control, in the Fast Lane
The modular Universal Drive Controller IP Core includes everything needed to control up to eight axes (i.e. motors) at control rates above 200 kHz, from the A/D converter interface to position, velocity and current controllers, position detection via encoder or resolver and control logic for power stages. DC, BLDC and 2- or 3-phase stepper motors are supported. Field-oriented control is available for brushless (BLDC) motors, and microstepping is supported for stepper motors.

Virtual Fifo, the Smart Way
The Stream Buffer Controller IP Core is optimized for FPGAs and implements a versatile Stream to Memory Mapped DMA bridge with up to 16 independent streams. The IP core allows data buffering in an external memory device to provide virtual FIFO capability with up to 4 GByte memory size. It provides an AMBA AXI4-Stream interface for each write and read data stream. A common memory-mapped master interface (AXI4 or Avalon) is provided to access the external memory device.

The IP core is highly configurable in terms of operation mode, buffer size and buffer address for each stream. The configuration is done over a memory-mapped slave interface, either by an embedded CPU, an FPGA Manager application or an application-specific stream configurator controller in VHDL.